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differential input, 1 msps 10-bit and 12-bit adcs in an 8-lead sot-23 ad7440/ad7450a rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features fast throughput rate: 1 msps specified for v dd o f 3 v an d 5 v low power at max throughput rate: 4 mw max at 1 msps with 3 v supplies 9.25 mw max a t 1 msps with 5 v s u pplies fully dif f erenti al analog input wide input bandwidth: 70 db sinad at 100 khz input frequency flexible power/serial clock speed managem e nt n o pipeline delays high speed s e r i al interface: spi?/qspi?/microwire?/dsp compatible power-down mode: 1 a m a x 8-lea d sot-23 and msop packages applications transducer int e rface battery-powered systems data acq u isitio n systems portable instrumentation motor control general d e scription the ad7440/ad7450a 1 a r e 10-b i t an d 12 -b i t hig h s p e e d , lo w p o w e r , successi v e a p p r o x im a t ion (sar) a n a l og -t o-d i g i t a l co n v er t e rs wi t h a f u l l y dif f er en t i al a n alog in p u t. th e s e p a r t s op e r a t e f r om a s i ng l e 3 v or 5 v p o we r supply an d u s e a d v a nc e d desig n te chniq u es to achie v e ve r y lo w p o w e r dissi p a t ion a t t h r o ug h p u t ra t e s u p t o 1 ms ps. the sar a r chi t e c t u r e o f t h es e p a r t s en s u r e s tha t t h er e a r e n o p i p e l i n e de l a ys. the p a r t s co n t ain a lo w n o is e , wid e b a n d wi d t h , dif f er en t i a l t r ack-and- h o ld a m plif ier (t /h) t h a t c a n hand le in p u t f r e q uen c ies u p to 3.5 mh z. th e r e fer e n c e v o l t a g e is a p plie d e x te r n a l ly to t h e v ref p i n and c a n be va r i e d f r o m 100 mv t o 3 . 5 v de p e nd ing on t h e p o we r su p p ly and w h a t su i t s t h e a p plic a t ion. th e val u e o f t h e r e fer e n c e v o l t a g e det e r m i n es t h e co mm o n - m o d e v o l t a g e ra n g e o f t h e p a r t . w i t h t h is t r u l y dif f er en t i al in put s t r u c t ur e a nd va r i a b le r e fer e nce in pu t, t h e us e r ca n s e le c t a va r i ety o f in p u t r a nges a nd b i as p o i n ts. the con v ersio n p r o c es s an d da t a acq u isi t ion a r e co n t r o l l e d usin g cs a nd t h e s e r i al c l o c k, al lo win g the device t o in t e r f ace w i t h m i c r opro c e ss or s or d s p s . t h e i n put s i g n a l s are s a m p l e d functional bloc k dia g ram 03051-a - 001 v ref t/h control logic 12-bit successive approximation adc gnd sclk sdata cs v dd ad7440/ad7450a v in+ v in? fi g u r e 1 . on t h e f a l l i n g e d ge of cs ; t h e con v ersio n is a l s o ini t ia t e d a t t h i s p o in t. th e sa r a r chi t e c t u r e o f t h es e p a r t s ens u r e s t h a t t h er e a r e n o p i p e line dela ys. th e ad7440 a nd t h e ad745 0a us e ad- va n c e d desig n te chniq u es to achie v e ver y lo w p o w e r dissi p a t i o n a t hig h thr o ug h p u t ra t e s. product highlights 1. o p era t ion w i t h ei t h er 3 v o r 5 v p o w e r s u p p li es. 2. h i g h t h r o ug h p u t w i t h lo w p o wer co n s um p t io n . w i t h a 3 v s u p p l y , th e ad7440/ad7450a o f f e r 4 mw max p o w e r co n s um p t io n f o r 1 ms ps thr o ugh p u t . 3. f u l l y dif f er en t i al a n alog in p u t. 4. flexi b le po w e r/ser i al c l o c k spee d m a na g e m e n t . the con v ersio n ra t e is de t e r m ine d b y t h e s e r i al clo c k, al lo win g t h e p o w e r t o b e r e d u c e d as t h e con v ersio n t i m e is r e d u ce d t h r o ug h t h e s e r i al cl o c k s p e e d in cr e a s e . th es e p a r t s als o fe a t ur e a sh u t down mo de t o maximize p o w e r e f f i c i e n c y at l o w e r t h r o u g hp u t r a t e s . 5. v a r i abl e volt age re fe re nc e i n put . 6. no p i p e l i n e d e l a y . 7. a c c u ra t e con t r o l o f t h e s a m p ling in st an t v i a a cs in p u t and onc e - o f f c o n v e r s i on c o n t ro l. 8. en o b > eig h t b i ts ty p i cal l y wi t h 100 mv r e f e r e n c e. 1 pr otected by u. s. patent number 6,681,332.
ad7440/ad7450a rev. b | page 2 of 28 table of contents ad7440Cspecifications .................................................................... 3 ad7450aCspecifications ................................................................. 5 timing specifications ....................................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 te r m i no l o g y .................................................................................... 10 ad7440/ad7450aCtypical performance characteristics ....... 12 circuit information ........................................................................ 15 converter operation .................................................................. 15 adc transfer function ............................................................. 15 typical connection diagram ................................................... 16 analog input ............................................................................... 16 driving differential inputs ........................................................ 18 digital inputs .............................................................................. 20 reference ..................................................................................... 20 single-ended operation ............................................................ 20 serial interface ............................................................................ 21 modes of operation ....................................................................... 23 normal mode .............................................................................. 23 power-down mode .................................................................... 23 power-up time .......................................................................... 24 power vs. throughput rate ....................................................... 24 microprocessor and dsp interfacing ...................................... 25 grounding and layout hints .................................................... 26 evaluating the ad7440/ad7450a performance ................... 26 outline dimensions ....................................................................... 27 ordering guide ............................................................................... 28 revision history 2/04data sheet changed from rev. a to rev. b added patent note .............................................................................. 1 1/04data sheet changed from rev. 0 to rev. a updated format.................................................................... universal changes to general description ....................................................... 1 changes to table 1 footnotes ............................................................. 3 changes to table 2 footnotes ............................................................. 5 changes to table 3 footnotes ............................................................. 7
ad7440/ad7450a rev. b | page 3 of 28 ad7440Cspecifications table 1. v dd = 2.7 v to 3.6 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.0 v; v dd = 4.75 v to 5.25 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.5 v; v cm 1 = v ref ; t a = t min to t max , unless otherwise noted. temperature range for b version C40c to +85c. parameter test conditions/comments b version unit dynamic performance f in = 100 khz signal-to-(noise + distortion) (sinad) 2 61 db min total harmonic distortion (thd) 2 C82 db typ C74 db max peak harmonic or spurious noise 2 C82 db typ C76 db max intermodulation distortion (imd) 2 fa = 90 khz, fb = 110 khz second-order terms C83 db typ third-order terms C83 db typ aperture delay 2 5 ns typ aperture jitter 2 50 ps typ full power bandwidth 2, 3 @ C3 db 20 mhz typ @ C0.1 db 2.5 mhz typ dc accuracy resolution 10 bits integral nonlinearity (inl) 2 0.5 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 10 bits 0.5 lsb max zero-code error 2 2.5 lsb max positive gain error 2 1 lsb max negative gain error 2 1 lsb max analog input full-scale input span 2 v ref 4 v in+ C v inC v absolute input voltage v in+ v cm = v ref v cm v ref /2 v v inC v cm = v ref v cm v ref /2 v dc leakage current 1 a max input capacitance when in tr ack-and-hold 30/10 pf typ reference input v ref input voltage v dd = 4.75 v to 5.25 v (1% tolerance for specified performance) 2.5 5 v v dd = 2.7 v to 3.6 v (1% tolerance for specified performance) 2.0 6 v dc leakage current 1 a max v ref input capacitance when in tr ack-and-hold 10/30 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 a max input capacitance, c in 7 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v; i source = 200 a 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 v min output low voltage, v ol i sink = 200 a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 7 10 pf max output coding twos complement
ad7440/ad7450a rev. b | page 4 of 28 parameter test conditions/comments b version unit conversion rate conversion time 888 ns with an 18 mhz sclk 16 sclk cycles track-and-hold acquisition time 2 sine wave input 200 ns max step input 290 ns max throughput rate 1 msps max power requirements v dd range: 3 v + 20%/C10%; 5 v 5% 2.7/5.25 v min/v max i dd 8 normal mode (static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 ma max v dd = 2.7 v to 3.6 v 1.45 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd = 5 v, 1.55 mw typ for 100 ksps 9 9.25 mw max v dd = 3 v, 0.6 mw typ for 100 ksps 9 4 mw max full power-down v dd = 5 v, sclk on or off 5 w max v dd = 3 v, sclk on or off 3 w max 1 common-mode voltage. the input signal can be centered on a dc common-mode voltage in the range specified in figure 28 and figu re 29. 2 see terminology section. 3 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time may cause t he converter to return an incorrect result. 4 because the input spans of v in+ and v inC are both v ref and are 180out of phase, the differential voltage is 2 v ref . 5 the ad7440 is functional with a refe rence input from 100 mv and for v dd = 5 v; the reference can range up to 3.5 v. 6 the ad7440 is functional with a refe rence input from 100 mv and for v dd = 3 v; the reference can range up to 2.2 v. 7 guaranteed by characterization. 8 measured with a midscale dc input. 9 see power vs. throughput section.
ad7440/ad7450a rev. b | page 5 of 28 ad7450aCspecifications table 2. v dd = 2.7 v to 3.6 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.0 v; v dd = 4.75 v to 5.25 v, f sclk = 18 mhz, f s = 1 msps, v ref = 2.5 v; v cm 1 = v ref ; t a = t min to t max , unless otherwise noted. temperature range for b version C40c to +85c. parameter test conditions/comments b version unit dynamic performance f in = 100 khz signal-to-(noise + distortion) (sinad) 2 70 db min total harmonic distortion (thd) 2 v dd = 4.75 v to 5.25 v, C86 db typ C76 db max v dd = 2.7 v to 3.6 v, C84 db typ C74 db max peak harmonic or spurious noise 2 v dd = 4.75 v to 5.25 v, C86 db typ C76 db max v dd = 2.7 v to 3.6 v, C84 db typ C74 db max intermodulation distortion (imd) 2 fa = 90 khz, fb = 110 khz second-order terms C89 db typ third-order terms C89 db typ aperture delay 2 5 ns typ aperture jitter 2 50 ps typ full power bandwidth 2, 3 @ C3 db 20 mhz typ @ C0.1 db 2.5 mhz typ dc accuracy resolution 12 bits integral nonlinearity (inl) 2 1 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 12 bits 0.95 lsb max zero-code error 2 6 lsb max positive gain error 2 2 lsb max negative gain error 2 2 lsb max analog input full-scale input span 2 v ref 4 v in+ C v inC v absolute input voltage v in+ v cm = v ref v cm v ref /2 v v inC v cm = v ref v cm v ref /2 v dc leakage current 1 a max input capacitance when in tr ack-and-hold 30/10 pf typ reference input v ref input voltage v dd = 4.75 v to 5.25 v (1% tolerance for specified performance) 2.5 5 v v dd = 2.7 v to 3.6 v (1% tolerance for specified performance) 2.0 6 v dc leakage current 1 a max v ref input capacitance when in tr ack-and-hold 10/30 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 a max input capacitance, c in 7 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v; i source = 200 a 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 v min output low voltage, v ol i sink = 200 a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 7 10 pf max output coding twos complement
ad7440/ad7450a rev. b | page 6 of 28 parameter test conditions/comments b version unit conversion rate conversion time 888 ns with an 18 mhz sclk 16 sclk cycles track-and-hold acquisition time 2 sine wave input 200 ns max step input 290 ns max throughput rate 1 msps max power requirements v dd range: 3 v + 20%/C10%; 5 v 5% 2.7/5.25 v min/v max i dd 8 normal mode (static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 ma max v dd = 2.7 v to 3.6 v 1.45 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd = 5 v, 1.55 mw typ for 100 ksps 9 9.25 mw max v dd = 3 v, 0.6 mw typ for 100 ksps 9 4 mw max full power-down v dd = 5 v, sclk on or off 5 w max v dd = 3 v, sclk on or off 3 w max 1 common-mode voltage. the input signal can be centered on a dc common-mode voltage in the range specified in figure 28 and figu re 29. 2 see terminology section. 3 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time may cause t he converter to return an incorrect result. 4 because the input spans of v in+ and v inC are both v ref and are 180 out of phase, the differential voltage is 2 v ref . 5 the ad7450a is functional with a refe rence input from 100 mv and for v dd = 5 v; the reference can range up to 3.5 v. 6 the ad7450a is functional with a refe rence input from 100 mv and for v dd = 3 v; the reference can range up to 2.2 v. 7 guaranteed by characterization. 8 measured with a midscale dc input. 9 see power vs. throughput section.
ad7440/ad7450a r e v. b | pa ge 7 o f 2 8 timing specifications g u a r an t e ed b y c h a r ac t e r i za tio n . al l in p u t sig n a l s a r e s p ecif ied wi t h tr = tf = 5 n s (10% t o 90% o f v dd ) and t i me d f r om a vol t age l e vel of 1.6 v . s e e f i gur e 2, f i gur e 3, a n d th e s e r i al i n t e r f ace s e c t ion. table 3. v dd = 2.7 v to 3.6 v, f scl k = 1 8 mhz, f s = 1 msps, v re f = 2. 0 v; v dd = 4.75 v to 5.2 5 v, f scl k = 1 8 mhz, f s = 1 ms ps, v re f = 2. 5 v; v cm 1 = v re f ; t a = t min to t max , unles s ot herwi s e not e d. parameter limit at t min , t ma x unit description f sclk 2 10 khz min 18 mhz max t con v ert 16 t sclk t sclk = 1/f sclk 888 ns max t qu iet 60 ns min minimum quiet time between the end of a se rial read and the next falling edge of cs t 1 10 ns min minimum cs pulse wid t h t 2 10 ns min cs falling edge to sclk falling edge setup time t 3 3 20 ns max delay from cs falling edge until s d ata three-state disabled t 4 3 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pulse width t 7 10 ns min sclk edge to da ta valid hold time t 8 4 10 ns min sclk falling edge to sdata three-state enabled 35 ns max sclk falling edge to sdata three-state enabled t power - up 5 1 s max power-up time from full power-down 1 common - m od e vo lt age. 2 mark/ s pace ratio for the sc lk input is 40/60 to 60/40. 3 mea s ure d with the loa d circuit o f a n d d e f i ne d as the time re quire d fo r the o u tput to cro s s 0.8 v or 2.4 v wi th v figu re 4 f i g ure 4. dd = 5 v or 0.4 v or 2.0 v for v dd = 3 v. 4 t 8 i s d e ri ved f r om t h e m e a s ur ed t i m e t a ken by t h e da t a o u t p ut s t o ch a n ge 0. 5 v wh en loa d ed wi t h t h e ci rcui t o f th e m e a s ured numbe r i s the n extrapo l ate d back to re mo ve the e f f e cts of charging o r d i s c harging the 25 pf capacito r. this me ans that the ti me , t 8 , quoted in the timing specif icat ions is the true bus rel i nquis h time of the part and is in d e pe nde nt o f the bus lo ad ing. 5 se e powe r- up ti m e s e ct i o n . t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk s dat a 4 leading zeros three-state 12 3 4 5 1 3 1 4 1 5 1 6 0 0 0 0 db11 db10 db2 db1 db0 b 03051-a - 002 f i g u re 2. a d 74 50a s e r i a l in ter f ac e tim i ng d i ag r a m t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk s dat a 4 leading zeros 2 trailing zeros three-state 12 3 4 5 1 3 1 4 1 5 1 6 0 0 0 0 db9 db8 db0 0 0 b 03051-a - 003 f i g u re 3. a d 74 40 s e ri al int e r f ace ti mi ng d i ag r a m
ad7440/ad7450a r e v. b | pa ge 8 o f 2 8 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 4. p a r a m e t e r r a t i n g v dd to gnd C0.3 v to +7 v v in+ to gnd C0.3 v to v dd + 0.3 v v inC to gnd C0.3 v to v dd + 0.3 v digital input voltage to gnd C0.3 v to +7 v digital output v o ltage to gnd C0.3 v to v dd + 0.3 v v ref to gnd C0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating tem p erature range commercia l (b version) C40c to +85c storage temperature range C65c to +150c junction tempe r ature 150c ja thermal imp e dance m s o p 2 0 5 . 9 c / w s o t - 2 3 2 1 1 . 5 c / w jc thermal imp e dance m s o p 4 3 . 7 4 c / w s o t - 2 3 9 1 . 9 9 c / w lead temperature, soldering vapor phase (60 secs) 215c infrared (15 secs) 220c e s d 1 k v s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . 1 transient currents of up to 100 ma do not cause s c r latch up. 03051-a - 004 1.6ma i ol 200 ai oh 1.6v to output pin c l 25pf f i gure 4 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng sp eci f ic ati o ns esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7440/ad7450a r e v. b | pa ge 9 o f 2 8 pin conf igurations and f u ncti on descriptions 03051-a - 005 v ref v in+ v in ? gnd 8 7 6 5 v dd 1 sclk 2 sdata 3 cs 4 ad7440/ ad7450a top view (not to scale) f i g u re 5. pin conf ig ur at i o n f o r 8-l e ad so t - 23 03051-a - 006 v dd sclk sdata cs 8 7 6 5 v ref 1 v in+ 2 v in ? 3 gnd 4 ad7440/ ad7450a top view (not to scale) f i gure 6. pin config ur ation f o r 8-l e ad msop ta ble 5. pi n f u nct i on d e s c ri pt i o ns mnemonic function v ref reference input for the ad7440 /ad7450a. an ex ternal refere nce must be appli e d to th is input. for a 5 v power supply, the reference is 2.5 v (1%) for spec ified performan c e. for a 3 v power supply, the reference is 2 v (1%) for specifi e d performan c e. t h is pin s h ould b e decoupled to gnd with a capa citor of at least 0.1 f. see the reference section for more d e tails. v in+ positive terminal for differential analog input. v inC negative terminal for di fferential analog input. gnd analog ground. ground reference point for all circuitry on the a d 7440/ad7450a. all analog in put signals and any external reference signal should be refe r r ed to this gnd voltage. cs chip select. acti ve low logic input. this input pr ovides the dual function of in itiating a conver si on on the ad7440/ad7450a and framing the serial data trans f er. sdata serial data. logi c output. the co nversion result from the ad7440/ad7450a is provided on this output as a serial data stream. the bits are clocked out on the f a lling edge of the sclk input. th e data stream of the ad7450a c o nsist s of four leading zeros followed by the 12 bits of conve r sion data, whi c h are provided msb first; the da ta stream of the ad7440 consist s of four lead ing zero s, fo llo wed by the 10 bits of convers i on d a ta, follo w e d by two trailing zeros. in both cases, the outpu t coding is twos complement. sclk serial clock. log i c input. sclk provides th e serial clock for accessing data from the part. t h is cloc k input is als o used as th e clock source for the conversi on proces s. v dd power supply input. v dd is 3 v (+20%/C10%) or 5 v (5%). this supply shou ld be decoupled to gnd with a 0.1 f capacitor and a 10 f tantalum capa citor i n paral l el.
ad7440/ad7450a rev. b | page 10 of 28 terminology signal-to-(noise + distortion) ratio t h i s i s t h e me a s u r e d r a t i o of s i g n a l to ( n oi s e + d i stor t i on ) a t t h e o u t p ut o f t h e a d c. th e sig n al i s t h e r m s am pli t ude o f t h e f u ndam e n t a l . n o is e is t h e sum o f a l l n o nf u ndam e n t a l sig n a l s u p t o half th e s a m p lin g f r e q ue nc y (f s /2), excl ud in g dc. th e ra ti o i s d e pen d en t o n t h e n u m b e r o f q u a n tiza tio n lev e ls i n t h e d i gi t i za ti o n p r o c e s s; th e m o r e lev e l s, th e sm alle r th e q u a n t i - z a ti o n n o i s e . t h e th eo r e tical si g n al- t o- (n o i se + d i s t o r ti o n ) ra ti o fo r a n ide a l n - b i t con v er t e r w i t h a si n e w a v e in p u t is g i v e n b y th e f o llo w i n g: sig n al - t o - ( n oi s e + d i s t or t i on ) = (6.02 n + 1.76)db . th us f o r a 12-b i t co n v er t e r , this is 74 db; an d f o r a 10-b i t co n v er t e r , this is 62 db . total harmoni c distortion (thd) t h d i s th e ra tio o f th e rm s s u m o f h a rm o n i c s t o th e f u ndam e n t al . f o r th e ad7440/ad7450a, i t is def i n e d as 1 2 6 2 5 2 4 2 3 2 2 v v v v v v thd + + + + = log 20 ) db ( w h er e v 1 i s th e rm s a m p l i t ud e o f th e fun d a m en tal a n d v 2 , v 3 , v 4 , v 5 , a n d v 6 a r e t h e r m s am pli t udes o f t h e s e c o nd t o t h e sixt h ha r m o n ics. peak harmoni c or spurious noise p e a k h a r m on i c ( s pu r i ou s noi s e ) i s t h e r a t i o of t h e r m s v a lu e of t h e n e xt l a rg es t co m p on e n t i n t h e ad c o u t p u t s p e c t r um (u p t o f s /2 an d excl udi n g dc) to t h e r m s va l u e o f t h e f u ndam e n t a l . n o r m a l ly , t h e v a l u e o f t h is sp e c if ica t ion is de t e r m i n e d b y t h e la rg es t ha r m oni c in t h e s p e c t r um, b u t fo r a d c s w h er e t h e ha r m o n ics a r e b u r i e d in t h e n o i s e f l o o r , i t is a no is e p e a k . intermodulati o n distortion w i t h in p u ts co nsis tin g o f sine wa v e s a t tw o f r e q uen c ies, fa a n d fb , a n y a c ti v e devi ce w i t h n o nli n ea ri ti e s cr ea t e s d i s t o r ti o n p r o d uc ts a t t h e sum and dif f er en ce f r e q ue n c ies o f mfa nfb wher e m, n = 0, 1, 2, 3, a n d s o on. i n ter m o d u l a t io n dist o r tio n t e r m s a r e th ose f o r whic h n e i t her m n o r n is eq ual t o 0. f o r ex a m ple, t h e s e c o nd-o r der ter m s in cl ud e (fa + f b ) a nd (fa C f b ), while t h e thir d-o r der t e r m s in c l ude (2fa + fb), (2fa C fb), (fa + 2fb), a nd (fa C 2fb). the ad7440/ad7450a is t e st e d usin g the cci f s t a n da r d o f tw o in p u t f r e q u e n c ies n e a r t h e t o p end o f t h e i n p u t b a n d wi d t h . i n t h is c a s e , t h e s e con d -o r d er t e r m s a r e dis t an c e d in f r e q uen c y f r o m t h e o r ig inal sin e wa v e s, w h i l e t h e t h ir d-o r der t e r m s a r e a t a f r e q uen c y clos e t o t h e in pu t f r e q uen c ie s. a s a r e s u l t , t h e s e con d - an d t h i r d-o r der ter m s a r e sp e c if ie d s e p a r a tely . t h e ca lc u l a t ion o f t h e i n ter m o d u l a t io n disto r t i o n is as p e r t h e t h d s p e c if ic a t ion, w h er e i t is t h e ra t i o o f t h e r m s s u m o f t h e i n d i v i d u al d i s t o r ti o n p r od uct s t o th e rm s a m p l i t ud e o f th e s u m o f t h e f u ndam e n t a ls, exp r es s e d in db . ap erture dela y this is t h e am oun t o f tim e f r o m the leadin g e d g e o f th e s a m p ling c l o c k un til t h e ad c ac t u al l y ta k e s t h e s a m p le . aperture jitter this is t h e s a m p le-t o-s a m p le v a r i a t ion i n t h e e f fe c t i v e p o in t in t i me a t w h ich t h e ac t u a l s a m p l e is t a k e n. full power bandwidth t h e full po w e r ba n d w id th o f a n ad c i s t h e in p u t f r eq ue n c y a t w h ich t h e a m pl i t ude o f t h e r e con s t r uc t e d f u ndam e n t al is r e d u ced b y 0.1 db o r 3 db f o r a f u l l -s cale in p u t. commo n- mode rejection rat i o (cmrr) t h e co mm o n -m ode r e jecti o n ra ti o i s th e ra ti o o f th e po w e r in t h e ad c o u t p u t a t f u l l -s cale f r eq uen c y , f , t o t h e p o w e r o f a 100 mv p-p sine wa ve a p p l ied to th e co mm on-m o d e v o l t a g e o f v in+ and v inC of f r e q u e nc y f s as fol l o w s: cmrr (db) = 1 0 log ( pf/ p f s ) pf is t h e p o w e r a t t h e f r e q ue n c y f in t h e a d c ou t p ut; pf s is t h e po w e r a t f r eq u e n c y f s in t h e ad c o u t p ut. in tegral non l i n earity (inl) this is t h e maxi m u m d e v i a t io n f r o m a st ra ig h t l i ne p a ssin g th r o ugh th e en d p o i n t s o f th e ad c tra n sf e r fun c ti o n . differe ntial no nlinearity (dn l ) this is t h e dif f er en ce b e tw e e n t h e m e as ur e d a nd t h e ide a l 1 ls b cha n ge b e tw e e n an y tw o ad jace n t co des i n t h e a d c. zero-code err o r this is t h e d e vi a t io n o f t h e mi d s ca le co d e t r a n s i t i o n (111...111 t o 000...000) f r o m the ideal v in + ? v in C (i .e ., 0 ls b).
ad7440/ad7450a rev. b | page 11 of 28 positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal v in+ C v inC (i.e., +v ref ? 1 lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal vin+ ? vinC (i.e., Cvref + 1 lsb), after the zero code error has been adjusted out. track-and-hold acquisition time the track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency f s . the frequency of this input varies from 1 khz to 1 mhz. psrr (db) = 10log( pf / pf s ) pf is the power at frequency f in the adc output; pfs is the power at frequency f s in the adc output.
ad7440/ad7450a rev. b | page 12 of 28 ad7440/ad7450aCtypical performance characteristics t a = 25c, f s = 1 ms ps, f sc l k = 18 mh z, unles s o t h e r w is e n o t e d. 75 70 65 60 55 10 100 1000 03051-a - 007 frequency (khz) s i nad (db) v dd = 5.25v v dd = 4.75v v dd = 3.6v v dd = 2.7v f i g u re 7. a d 74 50a sina d v s . a n al og i n put f r equenc y f o r v a r i ous sup p ly v o lt ag es 0 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 10 1000 100 10000 03051-a - 008 frequency (khz) cmrr (db) v dd = 3v v dd = 5v fi g u r e 8 . c m r r v s . fr e q u e n c y f o r v dd = 5 v and 3 v 0 ?120 ?2 0 ?4 0 ?6 0 ?8 0 ?100 0 100 200 300 400 500 600 700 800 900 1000 03051-a - 009 supply ripple frequency (khz) p s rr (db) 100mv p-p sinewave on v dd no decoupling on v dd v dd = 3v v dd = 5v f i g u r e 9 . p s r r v s . s u pp l y ripp le f r e q ue n c y w i t h o u t s u pp ly de c o u p l i n g 0 ?140 ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 100 200 300 400 500 03051-a - 010 frequency (khz) s nr (db) 8192 point fft f sample = 1msps f in = 100ksps sinad = +71.7db thd = ? 82db sfdr = ? 83db f i gure 10. ad7450a d y namic p e r f or manc e with v dd = 5 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 1024 2048 3072 4096 03051-a - 011 code dnl e rror (ls b ) f i g u re 11. t y pic a l d n l f o r t h e a d 74 50 a f o r v dd = 5 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 1024 2048 3072 4096 03051-a - 012 code inl e rror (ls b ) f i g u re 12. t y pic a l i n l f o r t h e a d 74 50 a f o r v dd = 5 v
ad7440/ad7450a rev. b | page 13 of 28 3.0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a - 013 v ref (v) change in dnl (ls b ) positive dnl nega tive dnl f i gure 1 3 . change in dnl vs . v ref f o r the ad74 50 a for v dd = 5 v 2.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 2.2 2.5 03051-a - 014 v ref (v) change in dnl (ls b ) positive dnl negative dnl f i gure 1 4 . change in dnl vs . v ref f o r the ad74 50 a for v dd = 3 v 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 0 0.5 1.0 1.5 2.5 2.0 3.0 3.5 03051-a - 015 v ref (v) change in inl (ls b ) positive inl negative inl f i gure 1 5 . change in inl vs . v ref for the ad7 450 a fo r v dd = 5 v 2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 0.5 1.0 1.5 2.0 2.2 2.5 03051-a - 016 v ref (v) change in inl (ls b ) positive inl negative inl f i gure 1 6 . change in inl vs . v ref for the ad7 450 a fo r v dd = 3 v 8 0 1 2 3 4 5 6 7 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a - 017 v ref (v) ze ro-code e rror (ls b ) v dd = 5v v dd = 3v f i gure 17. cha n ge i n zero - c ode e r ror v s . r e fer e nce v o ltag e for v dd = 5 v a n d 3 v for the ad7 450 a 12.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a - 018 v ref (v) e ffe ctiv e numbe r of bits v dd = 5v v dd = 3v f i gure 1 8 . change in enob vs . referenc e v o l t a g e fo r v dd = 5 v a n d 3 v fo r the ad74 50 a
ad7440/ad7450a rev. b | page 14 of 28 10,000 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 2044 2045 2046 2047 2048 2049 03051-a - 019 code 10,000 codes v in+ = v in ? 10,000 conversions f s = 1msps f i g u re 19. h i s t og r a m of 1 0 ,0 0 0 conver s i ons of a dc input f o r t h e a d 74 50a wit h v dd = 5 v 0 ?140 ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 100 200 300 400 500 03051-a - 020 frequency (khz) s nr (db) 8192 point fft f sample = 1msps f in = 100khz sinad = +61.6db thd = ? 81.7db sfdr = ? 83.1db f i gur e 2 0 . ad74 40 d y nami c p e r f or manc e wi th v dd = 5 v 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 256 512 768 1024 03051-a - 021 code dnl e rror (ls b ) f i g u re 21. t y pic a l d n l f o r t h e a d 74 40 f o r v dd = 5 v 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 256 512 768 1024 03051-a - 022 code inl e rror (ls b ) f i g u re 22. t y pic a l i n l f o r t h e a d 74 40 f o r v dd = 5 v
ad7440/ad7450a rev. b | page 15 of 28 circuit i n formation the ad7440/ad7450a a r e 10-b i t an d 12 -b i t fas t , lo w p o w e r , sin g le-s u p p l y , s u cces si v e a p p r o x ima t ion a n alog-t o-dig i tal co n v er t e rs (ad c s). the y can op era t e w i t h a 5 v o r 3 v p o w e r s u p p l y a nd a r e c a p a b l e o f thr o ug h p u t r a t e s u p to 1 ms ps w h en su p p lie d w i t h an 18 mhz scl k . t h e y r e q u ir e a n ext e r n a l re f e re nc e to b e a p p l i e d to t h e v ref p i n, w i t h t h e val u e o f t h e r e fer e n c e ch o s e n dep e nding o n t h e p o w e r su p p ly a n d w h a t su i t s t h e ap p l i c at i o n . w h en t h e y a r e o p era t e d wi t h a 5 v s u p p l y , t h e maxim u m r e fer e n c e t h a t c a n b e a p plie d is 3.5 v . w h e n t h e y a r e o p era t e d w i t h a 3 v supp l y , t h e m a x i m u m re f e re nc e t h at c a n b e a p p l i e d i s 2.2 v (s ee the ref e r e n c e s e c t io n). the ad7440/ad7450a ha ve an o n -c hi p dif f er en t i al trac k-an d- h o ld am plif ier , a successi v e a p p r o x ima t ion (sar ) ad c, and a s e r i al in t e r f ace , h o us e d in ei t h er a n 8-lead s o t - 23 o r a n msop p a cka g e . the s e r i al clo c k i n p u t acces s es da t a f r o m t h e p a r t a n d p r o v ides t h e clo c k s o ur ce fo r t h e s u cces si v e a p pr o x ima t ion ad c. th e ad7 440/ad7450 a f e a t ur e a p o w e r - do wn o p t i o n f o r r e d u ce d p o w e r co n s um p t io n b e tw e e n con v ersio n s. t h e p o w e r - do wn fe a t ur e is im ple m e n t e d ac r o ss t h e st and a r d s e r i a l i n t e r f ac e as des c r i b e d in t h e m o de s o f o p er a t ion s e c t ion . converter operation the ad7440/ad7450a a r e s u c c es si v e a p p r o x ima t ion ad cs b a s e d a r o u nd t w o ca p a ci t i ve d a cs. f i gur e 23 a nd f i gur e 24 sh o w si m p lif i e d s c h e m a t i cs o f t h e ad c in a c q u isi t io n and c o n v e r s i on ph as e, re sp e c t i vely . t h e a d c i s c o m p r i s e d of co n t r o l log i c, a n sar , an d tw o c a p a ci t i v e d a cs. i n f i gur e 23 (a cq ui si ti o n p hase), sw 3 i s c l os ed , sw1 and s w 2 a r e in p o si tio n a, th e co m p a r a t o r is he ld in a ba lan c e d con d i t io n, a nd t h e s a m p ling ca p a c i t o r a r ra ys acq u ir e t h e dif f er en t i al sig n al o n t h e in p u t. 03051-a - 023 v in+ v in ? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a f i g u re 23. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n (f igur e 24), sw3 o p e n s an d sw1 and sw2 m o v e t o p o si tion b , c a usin g the co m p a r a t o r t o beco m e un bala n c e d . b o th in p u t s a r e d i sco n n e c t ed o n ce t h e co n v ersio n b e g i n s . th e co n t r o l log i c a n d t h e cha r g e r e dis t r i - b u t i on d a cs a r e us e d to ad d and sub t r a c t f i xe d am o u n t s o f ch arge f r om t h e s a m p l i ng c a p a c i tor ar r a y s to b r i n g t h e c o m p a r - a t or b a c k i n to a b a l a nc e d c o nd i t i o n . whe n t h e c o m p ar a t or i s r e bala nce d , t h e co n v ersio n is com p let e . the co n t r o l log i c gen e r a tes t h e a d c s o u t p u t c o de. t h e o u t p u t i m p e dances o f t h e so u r c e s d r i v i n g th e v in + and t h e v inC pi ns m u s t b e m a tc he d ; o t h e r w i s e , th e tw o i n p u ts h a v e d i f f e r e n t set t li n g ti m e s, r e s u l t in g in er r o rs. 03051-a - 024 v in+ v in ? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a f i g u re 24. a d c co nvers i on p h as e adc tra n s f er func ti on the o u t p u t co din g f o r th e ad74 40/ad7450 a is tw os co m p le m e n t . th e desig n e d co de tra n si tio n s o c c u r a t s u cces si ve ls b val u es (1 l s b , 2 ls bs, an d s o o n ). the ls b size o f t h e ad7450a is 2 v ref /4096, a n d th e l s b size o f th e ad7440 is 2 v ref /1024. th e ideal tra n sf er c h a r ac t e r i s t ic o f th e ad7440/ad74 50a is sh o w n in f i gur e 25. 03051-a - 025 100...000 analog input (v in+ ? v in? ) 011...111 100...001 100...010 011...110 000...001 111...111 1 lsb 1lsb = 2 v ref /4096 ad7450a 1lsb = 2 v ref /1024 ad7440 +v ref ? 1 lsb ?v ref 0 lsb 000...000 adc code f i g u re 25. a d 7 4 4 0 / a d74 50a id ea l t r a n s f er cha r a c te ris t i c
ad7440/ad7450a rev. b | page 16 of 28 typical connection diagram f i gur e 26 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7440/ad74 50a f o r bo th 5 v a nd 3 v su p p l i es. i n this s e t u p , t h e g n d pin is co nne c t e d t o t h e a n alog g r o u n d plan e o f t h e sys t em. the v re f p i n is co nn ec ted t o ei t h er a 2. 5 v o r a 2 v de co u p le d r e feren c e s o ur ce, de p e ndi n g o n t h e p o w e r su p p ly , to s e t u p t h e a n alo g in p u t ra n g e . th e comm o n - m o d e v o l t a g e has t o be s e t u p ext e r n al l y a n d is t h e val u e o n w h ic h th e tw o in p u ts a r e cen t er e d . the co n v ersion r e su l t is o u t p u t i n a 16-b i t w o rd wi t h 4 leadin g zer o s f o llo w e d b y th e ms b o f the 12-b i t o r 10-b i t r e s u l t . th e 10-b i t r e s u l t o f the ad7440 is f o l l o w ed b y 2 tra i lin g zer o s. f o r m o r e det a i l s o n dr i v i n g t h e dif f er en t i a l in p u ts and s e t t i n g u p t h e c o mm on m o de , r e fer t o t h e dr i v i n g dif f er en t i al inp u t s s e c t i o n . 03051-a - 026 ad7440/ ad7450a 0.1 f 0.1 f 10 f v ref v dd v in+ sclk 3v/5v supply serial interface c/ p sdata cs gnd v in? 2v/2.5v v ref *cm is the common-mode voltage. cm* v ref p-p cm* v ref p-p f i g u re 26. t y pic a l conne c t io n d i ag r a m analog input the a n alog in p u t o f th e ad744 0/ad7450 a is f u l l y dif f er en tial . dif f er en t i al sig n als ha v e a n u m b er o f b e n e f i ts o v er sin g le- en ded si gn als, in c l udi n g n o i s e im m u ni ty b a se d o n th e device s c o m m on - m o d e re j e c t i o n , i m prove m e n t s i n d i s t or t i on p e r f or - ma nce, do ub ling o f t h e d e v i ce s a v a i la b l e d y nam i c r a n g e, an d f l ex i b i l i t y in i n pu t r a n g es and b i as p o i n ts. f i gure 27 def i n e s t h e f u l l y dif f er en tial a n alog in p u t o f th e ad7440/ad7450a. 03051-a - 027 v ref p-p v in+ v in? v ref p-p ad7440/ ad7450a common-mode voltage f i g u re 27. d i f f e r e nt ia l input d e f i nit i on s the am pli t ude o f t h e dif f er en t i al sig n al is t h e dif f er en ce be tw e e n t h e sig n als a p p l ie d t o th e v in+ and v inC pi ns (i .e ., v in+ C v inC ). v in+ a nd v in C a r e sim u l t an e o usl y dr i v en b y tw o sig n als e a c h o f a m p l i t ude v ref t h a t a r e 180 ou t o f p h as e . th e a m pli t ude o f t h e dif f er en t i al sig n al is t h er efo r e Cv ref to + v ref peak -t o- peak ( 2 v ref ). this is tr ue r e ga r d les s o f th e co mm on mo d e ( c m ) . the co mm on mo de is t h e a v erag e o f t h e t w o sig n als, t h a t is, (v in+ + v inC )/2 and is t h er efo r e t h e v o l t a g e t h a t t h e tw o in p u ts a r e cen t er e d on. this r e s u l t s i n t h e s p an o f e a ch in p u t b e in g cm v ref /2. this v o l t a g e h a s to b e s e t u p ext e r n a l ly , a n d i t s ra n g e va r i es w i t h v ref . a s t h e va l u e o f v ref in cr ea ses, th e co mm o n -m od e ra n g e d e cr ea se s. w h en d r i v i n g th e in p u t s w i t h a n am plif ier , t h e ac t u a l com m o n -mo d e ra n g e is det e r m i n e d b y t h e am plif ier s ou t p ut v o l t a g e s w i n g. f i gur e 28 a nd f i gur e 29 s h o w ho w th e co mm on-m o d e ra n g e typ i ca l l y va r i es wi t h v ref fo r b o t h a 5 v and a 3 v p o w e r su p p ly . the co mm on mo de m u st b e in t h is ra n g e t o guara n t e e t h e f u n c tio n al i t y o f th e ad7440 /ad7450a. f o r e a s e of u s e, t h e c o m m on m o d e c a n b e s e t up to e q u a l v ref , r e s u l t in g i n t h e dif f er en t i al sig n al b e in g v ref cen t er e d o n v ref . w h en a con v ersio n t a k e s pl ace , t h e comm o n mo de is r e je c t e d , r e su l t in g i n a vi r t ua l l y n o is e - f r e e sig n a l o f a m pl i t ud e Cv ref to +v ref , co rr es p o n d in g t o t h e dig i tal co des o f 0 t o 4096 in the cas e o f t h e ad7 450a an d 0 t o 1 024 in t h e ad7 440. 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 03051-a - 028 v ref (v) common-mode v o ltage (v ) 1.75v 3.25v common-mode range f i gure 28. input common-m ode r a ng e vs . v ref (v dd = 5 v and v ref ( m ax ) = 3. 5 v ) 2.5 0.5 1.0 1.5 2.0 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 03051-a - 029 v ref (v) common-mode v o ltage (v ) 1v 2v common-mode range f i gure 29. input common-m ode r a ng e vs . v ref (v dd = 3 v and v ref (m a x ) =2 v )
ad7440/ad7450a rev. b | page 17 of 28 f i g u re 3 0 show s e x am pl e s of t h e i n put s to v in+ and v inC fo r dif f er en t val u es o f v ref fo r v dd = 5 v . i t a l s o g i ves t h e max i m u m a nd mi ni m u m c o mm on- m o d e v o l t a g es fo r e a ch r e fer e n c e va l u e acco r d in g t o f i gur e 28. 03051-a - 030 common-mode (cm) cm min = 1v cm max = 4v reference = 2v v in? v in+ 2v p-p common-mode (cm) cm min = 1.25v cm max = 3.75v reference = 2.5v v in? v in+ 2.5v p-p f i g u re 30. e x a m pl e s of t h e a n al og inp u t s to v in+ and v in C fo r di ffer e nt v a l u es o f v ref fo r v dd = 5 v an a l og i n pu t st r u c t u r e f i g u re 3 1 show s t h e e q u i v a l e n t c i rc u i t of t h e an a l o g i n put s t r u c t ur e o f th e ad7440/ad74 50a. the f o ur dio d es p r o v ide es d p r o t ecti o n f o r th e a n alog i n p u t s . c a r e m u st be ta k e n t o e n s u r e th a t th e a n alog i n p u t si g n als n e v e r e x ceed th e s u p p l y ra ils b y m o r e tha n 300 mv . this ca us es t h es e dio d es t o b e com e fo r w a r d b i a s e d a nd st a r t co nd u c t i n g i n to t h e subst r a t e. t h es e dio d es c a n cond uc t u p to 10 m a w i t h o u t c a usi n g ir r e versi b le da ma g e t o t h e p a r t . th e ca p a c i to rs, c1 in f i gur e 31, a r e typ i cal l y 4 pf a n d can p r ima r i l y b e a t t r ib u t e d to p i n ca p a ci t a n c e. the r e sis t o r s a r e l u m p e d com p on en ts made u p o f th e on r e sis t an c e o f t h e s w i t ch es. the val u e o f t h e s e r e sis t o r s is ty p i cal l y a b o u t 100 ?. th e ca p a ci t o rs, c2, a r e the ad c s s a m p lin g ca p a c i t o rs a nd ha v e a ca p a ci tan c e o f 16 pf typ i cal l y . 03051-a - 031 c1 c2 r1 d d c1 c2 r1 d d v dd v dd v in+ v in? f i g u re 31. equiv a le nt a n al og input c i rcuit con v ers i on p h as e C s w itch es o p en; t r a c k phas e C s w itc h es closed f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f r om th e a n alog i n p u t si gn al th r o ugh th e use o f a n rc lo w - pa s s f i l t er o n t h e r e le v a n t a n a l og in p u t p i n s is r e co m m e nde d . i n a p plica - t i ons w h e r e h a r m on i c d i stor t i o n a n d s i g n a l - t o - noi s e r a t i o are cr i t ica l , t h e a n a l og in p u t sh o u l d b e dr i v e n f r o m a lo w im p e - dan c e s o ur ce . l a rge s o ur ce im p e dan c e s sig n if ic a n t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e a d c. this ma y ne ces s i t a t e t h e us e o f an in p u t b u f f er a m plif ier . th e ch o i ce o f o p a m p is a f u n c t i on o f t h e p a r t ic u l a r a p plica t ion. w h en n o am pli f ier is us e d t o dr i v e t h e a n alog in p u t, t h e s o ur ce im p e dan c e sh ou ld be limi t e d to lo w val u es. the maxim u m s o ur ce im p e dance dep e n d s on t h e am o u n t o f tot a l ha r m o n ic d i stor t i on ( t h d ) t h a t c a n b e t o l e r a te d. t h e t h d i n c r e a s e s a s t h e s o ur ce i m p e dan c e i n cr e a s e s, a nd p e r f o r ma nce deg r ades. f i g u re 3 2 show s a g r a p h of t h d ve r s u s t h e an a l o g i n put s i g n a l f r e q uen c y fo r dif f er en t s o ur ce im p e dances fo r v dd = 5 v . 0 ?100 ?8 0 ?6 0 ?4 0 ?2 0 10 100 1000 03051-a - 032 input frequency (khz) thd (db) t a = 25 c v dd = 5v r in = 1k ? r in = 510 ? r in = 10 ? r in = 300 ? f i g u re 32. th d v s . a n al og input f r equ e nc y f o r v a ri ous s o ur c e impeda nc es fo r v dd =5 v f i g u re 3 3 show s a g r a p h of t h e t h d ve r s u s t h e an a l o g i n put fr e q u e n c y f o r v dd o f 5 v 5% a nd 3 v + 20%/C10%, while s a m p ling a t 1 m s ps wi th a n sc lk o f 18 mh z. i n this c a s e , t h e s o ur ce im p e dance is 10 ? . ?5 0 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 ?6 5 ?6 0 ?5 5 10 100 1000 03051-a - 033 input frequency (khz) thd (db) t a = 25 c v dd = 2.7v v dd = 3.6v v dd = 5.25v v dd = 4.75v f i g u re 33. th d v s . a n al og input f r equ e nc y f o r 3 v and 5 v sup p ly v o lt ag es
ad7440/ad7450a rev. b | page 18 of 28 drivi n g dif f erenti al i n puts dif f er en t i a l op e r a t io n r e q u ir es v in+ and v inC t o be dr i v en sim u l t an eo us l y wi t h tw o eq ual sig n als tha t a r e 180 o u t o f phas e . th e comm on m o de m u st b e s e t u p ext e r n al l y a n d has a ra n g e d e t e r m in ed b y v ref , t h e p o we r su p p ly , and t h e p a r t ic u l ar a m plif ier us e d to dr i v e t h e ana l og in p u ts (s e e f i gur e 28 a nd f i gur e 29). dif f er en t i a l m o des o f o p era t io n w i t h ei t h er an ac o r dc in p u t p r o v ide t h e b e st thd p e r f o r ma n c e o v er a wi de f r e q u e nc y r a nge . b e c a u s e not a l l a p pl i c a t i o n s h a ve a s i g n a l p r e c o ndi t i one d fo r dif f er en t i a l o p er a t ion, t h er e is o f ten a ne e d to p e r f o r m sin g le-ende d-to - d if fer e n t ia l con v ersio n . differential a m plifier an ide a l m e t h o d o f a p pl yi n g di f f er en t i al dr i v e to t h e ad7440/ad74 50a is t o us e a dif f er en tial a m plif ier s u c h as the ad8138. this p a r t ca n be us e d as a sin g le-en d e d -t o-dif f er en t i al a m plif ier o r as a dif f er en t i al -t o- dif f er en t i al a m plif ier . i n b o t h cas e s, t h e a n alo g in p u t needs t o be b i p o la r . i t als o p r o v ides co m m o n - m o d e le v e l sh if t i n g and b u f f er in g o f t h e b i p o la r i n p u t sig n al . f i gur e 34 s h o w s h o w the ad8138 can b e us ed as a sin g le-e n d e d - t o-dif f er en t i al am plif ier . th e p o si t i v e an d nega t i ve o u t p u t s o f th e ad8138 a r e co nnec t e d t o th e r e sp ec ti v e in p u ts on t h e a d c v i a a p a i r of s e r i e s re s i stor s to m i n i m i z e t h e e f f e c t s of s w itc h e d c a p a c i t a nc e on t h e f r on t e n d of t h e a d c s . t h e rc lo w-p a s s f i l t er on eac h a n alog in p u t is r e commen ded in ac a p p l ic a t ion s t o r e m o v e hig h f r eq uen c y co m p onen ts o f the a n alog in p u t. th e a r c h i t ec t u r e o f th e ad8138 r e s u l t s in o u t p u t s tha t a r e v e r y hig h l y balan c e d o v er a wide f r eq uen c y ra n g e w i t h o u t r e q u i r in g ti gh tl y ma t c h e d e x t e rn al co m p o n en t s . i f th e a n alog in p u t s o ur ce being us ed has zer o im p e dan c e , al l fo ur r e sis t o r s (r g 1, r g 2, r f 1, a nd r f 2) s h o u ld b e th e s a m e . i f t h e s o ur ce h a s a 50 ? im p e dan c e a nd a 50 ? ter m ina t io n, fo r exa m ple , t h e val u e o f r g 2 sh o u ld b e in cr eas e d b y 25 ? t o b a lan c e t h i s p a ral l e l im p e dan c e o n t h e in p u t and t h us en s u r e th a t bo th t h e posi ti v e a n d n e ga ti v e a n alog i n p u ts h a v e t h e sa m e g a i n ( s e e fi g u re 3 4 ) . t h e output s of t h e a m pl i f i e r are p e r f e c t l y ma t c h e d , b a l a n c e d dif f er en t i al ou t p uts o f iden t i cal a m pl i t ude a nd a r e exac tl y 180 o u t o f p h as e . the ad8138 is s p ecif ie d wi t h +3 v , +5 v , a nd 5 v p o w e r su p p l i e s , b u t t h e b e st re su lts are ob t a i n e d w i t h a 5 v su p p ly . the ad8132 is a lo w e r cos t de vice tha t co u l d als o be us e d in t h is co nf igura t i o n w i t h slig h t d i f f er en ces in ch a r ac t e r i st ics t o th e ad8138 b u t wi t h simi la r p e r f o r ma n c e and o p era t ion. 03051-a - 034 +2.5v gnd ? 2.5v ad8138 51 ? r g 1 r s * c* c* r s * r g 2 r f 2 v ocm r f 1 3.75v v in+ v in? v ref 2.5v 1.25v 3.75v 2.5v 1.25v ad7440/ ad7450a *mount as close to the ad7440/ad7450a as possible and ensure high precision r s and c s are used. r s ?5 0 ? ; c ? 1nf r g 1 = r f 1 = r f 2 = 499 ? ; r g 2 = 523 ? external v ref (2.5v) f i g u re 34. u s ing t h e a d 8 1 3 8 as a si ng le -e nded- t o - d i f f e re nt ia l a m p lif ier
ad7440/ad7450a rev. b | page 19 of 28 op a m p p a i r an o p a m p p a ir ca n be us e d t o dir e c t l y co u p le a dif f er en t i al sig n al t o th e ad7440/ad7450a. the cir c ui t c o nf igura t io n s sh own i n f i gur e 35 a nd f i gur e 3 6 sh o w h o w a d u a l o p a m p can b e us e d t o con v er t a sin g le-e n d e d sig n al i n t o a dif f er en t i al sign al f o r bo th a b i p o la r an d un i p o l a r in p u t sign al , r e s p ecti v e l y . the v o l t a g e a p plie d t o p o i n t a s e ts u p t h e co mm on- m o d e vol t a g e. i n b o t h di a g r a m s , i t is c o nn e c te d in s o m e wa y to t h e re f e re nc e, but a n y v a lu e i n t h e c o m m on - m o d e r a nge c a n b e in p u t her e t o s e t u p th e comm on m o de . the ad8022 is a sui t ab le d u a l o p a m p t h a t co u l d b e us e d in t h is co nf igura t io n t o p r o v ide dif f er en tial dr i v e t o t h e ad7440 /ad7450a. t a k e ca r e w h en ch o o sin g t h e o p a m p; t h e s e le c t i o n dep e nds o n t h e r e q u ir e d p o w e r s u p p l y a nd sys t em p e r f o r m a n c e ob je c t i v es. the dr i v er cir c ui ts i n f i gur e 35 a nd f i gur e 36 ar e o p t i mi ze d fo r dc co u p lin g a p plica t ion s r e q u ir i n g b e st dist o r t i o n p e r f o r ma n c e. the cir c ui t conf igur a t io n sh ow n in f i gur e 35 co n v er ts a uni p ol a r , sin g le-en d e d sig n al in to a dif f er en tial sig n al . the dif f er en t i al o p a m p dr i v er c i r c ui t in f i gur e 36 is co nf igur e d to co n v er t and le vel shif t a sin g l e -e n d e d , g r o u nd-r e fer e n c e d (b i p ola r ) sig n al t o a dif f er en t i al sig n al cen t er e d a t t h e v ref le ve l of t h e a d c . 03051- a- 036 v dd 2 v ref p-p v ref gnd 390 ? 220 ? 220 ? 220 ? 10k ? 27 ? 27 ? 0.1 f v+ v? v+ v? a v in+ v in? v ref ad7440/ ad7450a external v ref f i gure 3 5 . dua l o p a m p cir c ui t to co nv er t a single-ended uni p ola r si gna l int o a d i f f e r e nt ia l s i g n a l 03051-a-035 gnd v+ v? v+ v? a v in+ v dd v in ? v ref ad7440/ ad7450a 2 v ref p-p 390 ? 220 ? 220 ? 220 ? 220 ? 10k ? 20k ? 27 ? 27 ? 0.1 f external v ref f i gure 3 6 . dua l o p a m p cir c ui t to co nv er t a single -ende d bipolar sign al into a d i f f e r e nt ia l s i g n a l rf t r a n sforme r a n r f tra n sf o r m e r w i t h a cen t e r ta p o f f e r s a g ood so l u ti o n f o r ge ne r a t i ng d i f f e r e n t i a l i n put s i n s y ste m s t h a t d o not ne e d to b e d c - c oupl e d . f i g u re 3 7 show s how a t r ans f or me r i s u s e d f o r sin g le-e n d e d - t o-dif f er en t i al con v ersio n . i t p r o v ides t h e b e n e f i ts o f o p era t in g t h e ad c in t h e dif f er en t i a l m o de w i t h ou t co n t r i - b u tin g a d di ti o n al n o i s e a n d d i s t o r ti o n . a n r f tra n sf o r m e r also has t h e b e nef i t o f p r o v idin g e l e c t r ica l is ola t ion b e tw e e n t h e sig n al s o ur ce and the a d c. a tr a n sfo r m e r ca n be us e d fo r m o st ac a p plic a t ion s . the ce n t er t a p is us e d t o shif t t h e dif f er en t i a l sig n a l t o t h e comm on- m o d e l e v e l r e q u ir e d ; i n t h is cas e , i t is co nne c t e d t o t h e r e fer e n c e s o t h e comm o n - m o d e le ve l is t h e val u e o f t h e r e fe r e n c e . 03051-a - 037 r r c 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v r v in+ v in? v ref ad7440/ ad7450a external v ref f i g u re 37. u s ing an r f t r ans f or me r t o gener a t e d i f f e r e nt i a l i n put s
ad7440/ad7450a rev. b | page 20 of 28 digi tal in p u ts the dig i t a l i n p u ts a p plie d to t h e de vice a r e n o t limi te d b y t h e max i m u m ra t i ngs, w h ich lim i t t h e ana l o g limi ts . i n ste a d t h e dig i t a l in p u ts a pplie d , cs a n d s c l k , ca n go to 7 v a nd a r e n o t r e s t ri ct ed b y th e v dd + 0.3 v limi ts as on t h e a n a l og in p u t. the ma i n ad van t a g e o f t h e i n pu ts n o t b e in g r e s t r i c t e d t o t h e v dd + 0 . 3 v l i m i t is t h a t p o we r su p p ly s e qu e n c i ng issu e s are av o i d e d . if cs an d sclk a r e a p plie d b e fo r e v dd , t h er e is n o r i s k o f la t c h-u p as t h er e w o u l d be on the a n alog in p u ts if a sig n al g r ea t e r tha n 0.3 v was a p p l ie d p r io r t o v dd . reference a n e x te r n a l re f e re nc e s o u r c e i s r e qu i r e d to supp ly t h e re f e re nc e t o th e de vice . this r e f e r e n c e in p u t can ra n g e f r o m 100 mv t o 3.5 v . w i t h a 5 v p o w e r s u p p l y , th e sp ecif ie d r e f e r e n c e is 2.5 v a nd t h e maxim u m r e f e r e n c e is 3.5 v . w i t h a 3 v p o w e r s u p p l y , t h e s p e c i f i e d re f e re nc e i s 2 v a n d t h e m a x i m u m re f e re nc e i s 2.2 v . i n bo th cas e s, th e r e f e r e n c e is f u n c tio n a l f r o m 100 mv . e n su re t h at , w h e n c h o o s i ng t h e re f e re nc e v a lu e f o r a p a r t i c u l ar a p plic a t ion, t h e maxim u m a n a l og in p u t ra n g e ( v in max ) is n e v e r gr ea t e r tha n v dd + 0.3 v t o co m p l y wi th t h e maxim u m ra t i n g s o f t h e de v i ce . th e fol l o w i n g tw o exam ples calc u l a t e t h e max i m u m v ref i n p u t th a t ca n b e used w h en o p e r a t i n g t h e ad7440/ad74 50a a t a v dd o f 5 v a nd 3 v , r e sp ec ti v e l y . ex a m ple 1 v in max = v dd + 0.3 v in max = v re f + v ref /2 if v dd = 5 v , th en v in ma x = 5.3 v . ther efo r e 3 v ref /2 = 5.3 v v ref max = 3.5 v t h us , w h en o p era t i n g a t v dd = 5 v , t h e val u e o f v ref ca n ra n g e f r o m 100 mv t o a maxim u m val u e o f 3.5 v . w h en v dd = 4.75 v , v ref max = 3.17 v . ex a m ple 2 v in max = v dd + 0.3 v in max = v re f + v ref /2 if v dd = 3 v , th en v in ma x = 3.3 v . ther efo r e , 3 v ref /2 = 3.3 v v ref max = 2.2 v t h us , w h en o p era t i n g a t v dd = 3 v , t h e val u e o f v ref can ra n g e f r o m 100 mv t o a maxim u m val u e o f 2.2 v . w h en v dd = 2.7 v , v ref max = 2 v . th e s e exa m ples s h o w t h a t t h e maxim u m r e fer e n c e a p pli e d t o th e ad7440 /ad7450a is dir e c t l y dep e nden t on the val u e ap p l i e d t o v dd . the val u e o f t h e r e fer e n c e s e ts t h e analog in p u t s p a n and t h e c o m m on - m o d e vo lt age r a ng e. e r ror s i n t h e re f e re nc e s o u r c e r e s u l t in ga in er r o rs in th e ad7 440/ad7450 a t r a n sf er f u n c tio n a nd ad d to sp e c if ie d f u l l -s ca le e r r o rs o n t h e p a r t . a 0.1 f c a p a c i tor s h ou l d b e u s e d to de c o upl e t h e v ref pin to g n d . f i gur e 38 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e v ref pi n . t a b l e 6 lis t s exam ples o f s u i t ab le v o l t a g e r e fer e n c es. 03051-a - 038 1 ad780 nc 8 2 v in nc 7 3 gnd 6 4 temp 5 opsel trim v out ad7440/ ad7450a* v ref 2.5v nc v dd nc v dd nc = no connect 10nf 0.1 f 0.1 f 0.1 f *additional pins omitted for clarity f i g u re 38. t y pic a l v ref c o nnec t ion d i agr a m for v dd = 5 v table 6. exa m ples of suitable voltage re fere nces reference ou tpu t voltage (v) initial accu racy (%) operating current (a) ad780 2.5/3 0.04 1000 adr421 2.5 0.04 500 adr420 2.048 0.05 500 single-ended opera t i o n w h en su p p lie d wi t h a 5 v p o w e r s u p p l y , th e ad7440/ad7450 a ca n h a n d le a si ng le-e n d e d in p u t . th e desig n o f t h es e de vices is o p t i mi ze d fo r dif f er en t i al o p er a t io n, s o w i t h a si n g le-e n d e d in p u t, p e r f o r ma n c e deg r ades. l i n e a r i t y deg r ade s b y typ i cal l y 0.2 ls b , the f u l l -s cale er r o rs deg r ade typ i cal l y b y 1 ls b , a nd ac p e r f or m a nc e i s not g u ar an te e d . t o o p er a t e t h e ad7440/ad74 50a in sin g le-en d e d m o de , the v in+ i n p u t is cou p le d t o t h e sig n al s o ur ce , w h i l e t h e v inC in p u t is b i as e d t o t h e a p p r o p r i a t e v o l t a g e co r r es p o n d ing t o t h e mids cal e co de t r a n s i t i o n . this v o l t a g e is t h e com m o n m o de , w h ich is a f i xe d dc v o l t a g e (us u al l y t h e r e fer e n c e). th e v in+ in p u t s w in gs arou nd t h i s v a lu e an d s h ou l d h a ve a volt age sp an of 2 v ref to mak e us e o f t h e f u l l d y na mic ran g e o f t h e p a r t . the i n p u t sig n a l t h er efo r e has p e ak-t o- p e a k val u es o f co mm on m o de v ref . i f t h e an a l o g i n put i s u n i p o l ar , an op am p i n a non i n v e r t i ng u n it y ga in co nf igur a t i o n can b e us e d to dr i v e t h e v in+ pi n . t h e a d c op e r a t e s f r om a s i ng l e su p p ly , s o i t is ne c e ss ar y to l e vel shif t gr o u n d -ba s ed b i po l a r s i gn al s t o c o m p l y wi th th e i n p u t r e q u ir em e n ts. a n o p a m p can b e co nf igur e d to r e s c a l e an d l e vel s h i f t th e gr o u n d - b a s ed b i po l a r s i gn al , so i t i s c o m p a t i b l e wi th th e s e lec t e d in p u t ra n g e o f the ad7440/ad74 50a (f igur e 39).
ad7440/ad7450a rev. b | page 21 of 28 03051-a - 039 r 5v 2.5v 0v +2.5v 0v ? 2.5v r r 0.1 f r ad7440/ ad7450a v ref v in+ v in ? v in external v ref (2.5v) f i gure 39. a p plying a b i polar s i ng le -e nded input to the a d 7 440 / a d7 45 0 a serial interface f i gur e 2 a nd f i gur e 3 sh o w det a i l e d t i min g di ag r a m s fo r t h e s e r i al in t e r f ace o f th e ad7450 a an d t h e ad7 440, r e s p ec ti v e l y . the s e r i al clo c k p r o v ides t h e con v ersio n clo c k and als o co n t r o ls t h e t r a n sfer o f da t a f r o m t h e de vices d u r i n g con v ersio n . cs ini t i a t e s t h e con v ersio n p r o c es s a nd f r a m es t h e da t a t r an sfer . the fa l l in g e d ge o f cs p u ts t h e t r ack-and- h o ld i n t o h o ld m o d e a nd t a k e s t h e b u s o u t o f t h r e e-st a t e. t h e ana l o g in p u t is s a m p l e d a nd t h e con v ersio n is in i t ia t e d a t t h is p o i n t. t h e co n v ersio n r e q u ir es 16 scl k c y cles t o co m p let e . on ce 13 s c lk f a l l in g e d ges h a ve o c c u r r e d , t h e t r ack-and- h o ld go es b a ck i n t o t r ack o n t h e n e xt sclk r i sin g e d ge, as sh o w n a t p o in t b in f i gur e 2 a nd f i gur e 3 . on th e 16t h s c lk fal l ing edge , t h e sd a t a li ne g o es b a ck i n t o t h r e e-s t a t e . i f t h e r i sin g e d g e o f cs o c c u rs bef o r e 16 sclks ha v e e l a p s e d , th e con v ersio n t e r m ina t es an d t h e sd a t a li ne g o es b a ck i n t o t h r e e-s t a t e . the con v ersio n r e s u l t f r o m th e ad7440/ad74 50a is p r o v ide d on t h e sd a t a output a s a s e r i a l d a t a st re am . t h e bit s are clo c k e d o u t on t h e fal l i n g e d ge o f t h e scl k in pu t. th e da t a s t r e a m o f the ad7450a co n s is ts o f f o ur leadin g zer o s f o l l o w ed by 1 2 bit s of c o n v e r s i on d a t a prov i d e d m s b f i r s t ; t h e d a t a s t r e a m o f the ad7440 co n s is ts o f f o ur leadin g zer o s, f o l l o w ed b y t h e 1 0 bit s of c o n v e r s i on d a t a f o l l owe d by t w o t r ai l i ng z e ro s , w h ich is a l s o p r o v ide d m s b f i rst. i n b o t h cas e s, t h e o u t p ut co din g is tw os c o m p lem e n t . sixt e e n s e r i al cl o c k c y cles a r e r e q u ir e d t o p e r f o r m a con v ersio n a nd access da t a f r o m th e ad74 40/ad7450 a. cs going l o w p r o v ides t h e f i rst le adin g zer o t o b e r e a d in b y t h e ds p o r micr o c o n t r ol ler . the r e ma in in g d a t a is t h e n clo c k e d o u t on t h e s u b s eq u e n t sc l k f a l l i n g ed g e s b e gi n n i n g w i th t h e se c o n d le adin g zer o . th us, t h e f i rst fa l l i n g clo c k e d ge on t h e s e r i a l clo c k p r o v ides t h e s e c o nd le adi n g z e r o . th e f i na l b i t i n t h e da t a tra n s f e r i s v a l i d o n th e 16th fall in g ed g e , ha v i n g been c l ock e d out on t h e pr e v i ou s ( 1 5 t h ) f a l l i n g e d ge. o n c e t h e c o n v e r s i o n i s c o m p l e t e a n d th e d a ta h a s b e e n a c c e s s ed a f t e r th e 1 6 c l oc k c y cles, i t is im p o r t a n t t o en s u r e t h a t b e fo r e t h e n e xt con v ersio n is ini t i a t e d , e n oug h t i m e is lef t t o m e e t t h e acquisi t io n and q u iet t i m e sp e c i f ica t io n s (s e e t i min g e x a m ples 1 a nd 2). t o achie v e 1 ms ps wi t h an 18 mhz clo c k fo r v dd = 3 v a nd 5 v , an 18-clo c k b u rst p e r f o r m s t h e con v ersio n a nd le a v es en o u g h t i m e b e fo r e t h e n e xt co n v ersio n fo r t h e ac q u isi t ion and q u iet t i m e . i n a p plic a t io n s wi t h a slo w er sclk, i t ma y b e p o ssi b le t o r e a d in da ta o n ea ch scl k ri si n g ed g e ; th a t i s , th e f i r s t ri si n g ed g e o f sclk a f t e r th e cs fa l l in g e d ge w o u l d ha v e t h e le a d in g zer o p r o v i d ed a n d t h e 15th sc lk edg e w o ul d h a v e d b 0 p r o v i d ed . 03051-a - 040 t 2 t 8 t 6 t 5 t convert cs sclk 12 3 4 5 1 3 1 4 1 5 1 6 12.5(1/f sclk ) t acquisition 1/throughput t quiet 10ns b c f i gure 40. s e ri al inter f ace ti ming e x a m pl e
ad7440/ad7450a rev. b | page 22 of 28 timing example 1 having f sclk = 18 mhz and a throughput rate of 1 msps gives a cycle time of 1/ throughput = 1/1,000,000 = 1 s a cycle consists of t 2 + 12.5(1/ f sclk ) + t acq = 1 s therefore, if t 2 = 10 ns 10 ns + 12.5(1/18 mhz) + t acq = 1 s t acq = 296 ns this 296 ns satisfies the requirement of 290 ns for t acq . from figure 40, t acq comprises 2.5(1/ f sclk ) + t 8 + t quiet where t 8 = 35 ns. this allows a value of 122 ns for t quiet , satisfying the minimum requirement of 60 ns. timing example 2 having f sclk = 5 mhz and a throughput rate of 315 ksps gives a cycle time of 1/ throughput = 1/315,000 = 3.174 s a cycle consists of t 2 + 12.5(1/ f sclk ) + t acq = 3.174 s therefore, if t 2 is 10 ns 10 ns + 12.5(1/5 mhz) + t acq = 3.174 s t acq = 664 ns this 664 ns satisfies the requirement of 290 ns for t acq . from figure 40, t acq comprises 2.5(1/ f sclk ) + t 8 + t quiet where t 8 = 35 ns. this allows a value of 129 ns for t quiet , satisfying the minimum requirement of 60 ns. as in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 60 ns minimum t quiet between conversions. in timing example 2, the signal should be fully acquired at approximately point c in figure 40.
ad7440/ad7450a rev. b | page 23 of 28 modes of operation the o p er a t io nal m o de o f th e ad7440/ad7450a is s e lec t ed b y co n t r o l l in g t h e log i c s t a t e o f t h e cs si gn al d u ri n g a co n v er si o n . ther e a r e tw o p o s s i b le m o des of o p era t io n, n o r m al an d p o w e r do wn. t h e p o i n t a t w h ich cs is p u l l e d hig h a f t e r t h e con v ersion has b e en i n i t i a te d de t e r m i n es w h et her o r n o t t h e de vice e n t e rs p o w e r - do w n mo de. simi la rly , if a l r e ad y in p o wer - do w n , cs co n t r o ls w h et h e r t h e de vices r e t u r n t o n o r m al op era t ion o r r e ma in i n p o w e r - do w n . th es e m o de s o f o p era t io n a r e desig n e d to prov i d e f l e x ibl e p o we r m a n a ge me n t opt i ons . t h e s e opt i o n s ca n b e ch o s e n to o p t i mi ze t h e p o w e r dissi p a t i o n/t h r o ug h p u t ra t e ra t i o f o r d i f f er in g a p p l ica t io n r e q u ir em en ts. normal m o de this m o d e is in t e nde d fo r fast e s t t h r o ug h p ut ra t e p e r f o r ma n c e . the us er do es no t ha v e t o w o r r y a b o u t an y p o w e r - u p t i m e s w i t h th e ad7440 /ad7450a r e ma inin g f u l l y p o w e r e d u p al l the time . f i g u re 4 1 show s t h e ge ne r a l d i a g r a m of t h e op e r a t i o n of t h e ad7440/ad74 50a in this m o de . th e con v ers i o n is ini t ia t e d on th e fal l in g edge o f cs , a s d e sc ri bed i n th e se rial i n t e rf a c e s e c t i o n . t o e n su re t h e p a r t re m a i n s f u l l y p o we re d up , cs mu s t r e ma in lo w un ti l a t le ast 10 scl k fal l in g e d g e s ha v e el a p s e d af te r t h e f a l l i n g e d ge of cs . 03051-a - 041 11 0 cs sclk sd a t a 16 4 leading zeros + conversion result f i g u re 41. no r m a l m o de o p er at io n if cs i s b r o u gh t h i gh a n y tim e a f t e r th e 1 0 t h s c lk f a ll i n g ed g e , b u t be f o r e th e 16th sc l k falli n g ed g e , t h e pa r t r e m a i n s p o w e r e d u p b u t t h e con v ersio n t e r m ina t es an d s d a t a g o es ba c k in t o th r ee-s t a t e . s i xt een seri al c l oc k c y c l e s a r e r e q u i r ed t o co m p let e t h e con v ersio n and ac ces s the co m p let e con v ersio n re su lt . cs ma y idle hig h un til t h e next co n v ersio n o r ma y idle lo w un til so m e t i m e p r i o r t o th e n e xt co n v e r si o n . o n ce a da ta tra n sfer is co m p let e , w h en s d a t a has r e t u r n e d t o thr e e-s t a t e , a n o t h e r co n v e r si o n ca n be in i t ia t e d a f t e r th e q u ie t tim e , t qu iet , has el a p s e d b y aga i n b r in g i n g cs lo w . power-down mode this m o d e is in t e nde d fo r us e in a p pli c a t io n s w h er e slo w er th r o ugh p u t ra t e s a r e r e q u i r ed ; ei th e r t h e a d c i s po w e r e d d o wn b e t w e e n e a c h c o n v e r s i on , or a s e r i e s of c o n v e r s i ons m a y b e p e r f o r m e d a t a hig h t h r o ug h p ut r a te and t h e a d c is t h en p o w e r e d do w n fo r a r e la t i vely lon g d u r a t i o n b e t w e e n t h es e b u rs ts o f con v ersio n s. w h en t h e ad7440/ad74 50a a r e in t h e p o w e r - do w n mo de, a l l a n a l o g cir c ui t r y is p o w e r e d do w n . t o en t e r p o w e r - do w n m o de , t h e c o n v ersio n p r o c e s s m u s t b e i n te r r upte d b y b r i n g i ng cs hig h an y w h e r e a f t e r th e s e con d fal l in g edg e o f s c lk and bef o r e th e 10th f a l l in g edg e o f sclk, a s s h ow n i n fi g u re 4 2 . 03051-a - 042 1 10 sclk s dat a three-state 2 cs f i gure 42. enter i ng p o w e r - d o wn mod e on ce cs h a s been b r o u gh t hi gh in th i s w i n d o w o f s c l k s , th e p a r t en t e rs p o w e r - do w n , t h e con v ersio n t h a t w a s ini t i a te d b y th e fal l in g edge o f cs is t e r m ina t e d , a nd sd a t a go es b a ck i n t o th r e e - s t a t e . th e ti m e f r o m th e ri si n g ed g e o f cs to sd a t a t h r e e-s t a t e ena b le d is ne v e r g r e a t e r t h a n t 8 (r efer t o t h e t i min g s p e c if ic a t io n s ). i f cs i s b r o u gh t h i gh be f o r e th e s e c o n d s c lk fa l l in g e d ge, t h e p a r t r e ma in s in n o r m a l m o de and do es n o t p o w e r do wn. t h is a v o i ds a c cid e n t a l p o w e r - do w n d u e to g l i t ches on t h e cs lin e . i n o r der to ex i t t h is m o de o f o p er a t io n a nd p o w e r u p t h e ad7440/ad74 50a a g a i n, a d u mm y con v ersion is p e r f o r m e d . on t h e fal l in g e d g e o f cs , t h e d e vi ce b e g i n s to p o w e r u p a nd co n t in ues t o p o w e r u p as lo n g as cs is h e l d lo w un til a f t e r the fall i n g ed g e o f t h e 10t h sc lk . t h e devi ce i s fu ll y po w e r e d u p a f ter 1 s has el a p s e d an d , as sho w n i n f i gur e 4 3 , va lid d a t a r e s u l t s f r o m th e n e xt con v ersion. 03153-a - 031 cs sclk sdata 1 10 1 6 1 1 0 1 6 a this part is fully powered up with v in fully acquired part begins to power up invalid data valid data t power-up f i g u re 43. e x it ing p o wer - d o wn m o de
ad7440/ad7450a rev. b | page 24 of 28 if cs is brought high before the 10th falling edge of sclk, the ad7440/ad7450a again goes back into power-down. this avoids accidental power-up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. so although the device may begin to power up on the falling edge of cs , it again powers down on the rising edge of cs as long as it occurs before the 10th sclk falling edge. power-up time the power-up time of the ad7440/ad7450a is typically 1 s, which means that with any frequency of sclk up to 18 mhz, one dummy cycle is always sufficient to allow the device to power up. once the dummy cycle is complete, the adc is fully powered up and the input signal is acquired properly. the quiet time, t quiet , must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of cs . when running at the maximum throughput rate of 1 msps, the ad7440/ad7450a power up and acquire a signal within 0.5 lsb in one dummy cycle, 1 s. when powering up from the power-down mode with a dummy cycle, as in figure 43, the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 43. although at any sclk frequency one dummy cycle is sufficient to power up the device and acquire v in , it does not mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1 s is sufficient to power up the device and acquire the input signal. for example, if a 5 mhz sclk frequency was applied to the adc, the cycle time would be 3.2 s (1/(5 mhz) 16). in one dummy cycle, 3.2 s, the part would be powered up and v in acquired fully. however, after 1 s with a 5 mhz sclk, only five sclk cycles would have elapsed. at this stage, the adc would be fully powered up and the signal acquired. so in this case, the cs can be brought high after the 10th sclk falling edge and brought low again after a time, t quiet , to initiate the conversion. when power supplies are first applied to the device, the adc may power up in either power-down mode or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if the user wants the part to power up in power-down mode, the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as the one shown in figure 42. once supplies are applied to the ad7440/ad7450a, the power- up time is the same as that when powering up from power- down mode. it takes about 1 s to power up fully if the part powers up in normal mode. it is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, ensure that adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first sclk edge applied after the falling edge of cs . however, when the adc powers up initially after supplies are applied, the track-and-hold is already in track mode. assuming the user has the facility to monitor the adc supply current, this means the adc powers up in the desired mode of operation, and thus a dummy cycle is not required to change mode. a dummy cycle is therefore not required to place the track-and-hold into track mode. power vs. throughput rate by using the power-down mode on the ad7440/ad7450a when not converting, the average power consumption of the adc decreases at lower throughput rates. figure 44 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption is reduced accordingly for both 5 v and 3 v power supplies. for example, if the ad7440/ad7450a are operated in continuous sampling mode with a throughput rate of 100 ksps and an sclk of 18 mhz, and the device is placed in power- down mode between conversions, the power consumption is calculated as follows: power dissipation during normal operation = 9.25 mw max (for v dd = 5 v) if the power-up time is one dummy cycle (1 s), and the remaining conversion time is another cycle (1 s), the ad7440/ad7450a can be said to dissipate 9.25 mw for 2 s 1 during each conversion cycle. if the throughput rate = 100 ksps, the cycle time = 10 s and the average power dissipated during each cycle is (2/10) 9.25mw = 1.85 mw . for the same scenario, if v dd = 3 v, the power dissipation during normal operation is 4 mw max. the ad7440/ad7450a can now be said to dissipate 4 mw for 2 s 1 during each conversion cycle. 1 this figure assumes a very short time to enter power- down mode. this increases as the burst of clocks used to enter this mode is increased.
ad7440/ad7450a rev. b | page 25 of 28 th us, t h e a v er ag e p o w e r dis s i p a t e d d u r i n g e a ch c y cle wi t h a thr o ug h p u t ra t e o f 100 ks ps is (2/10) 4 mw = 0.8 mw . this is h o w t h e p o w e r n u m b ers in f i gur e 44 a r e ca lc u l a t e d . f o r thr o ug h p u t ra t e s abo v e 320 ks ps, i t is r e commende d t o r e d u ce t h e ser i a l c l o c k f r eq uen c y f o r bes t p o w e r p e r f o r ma n c e . 03051-a - 044 throughput (ksps) 100 0 350 p o we r (mw) 0.01 50 100 150 200 250 300 0.1 1 10 v dd = 5v v dd = 3v f i gure 44. p o wer v s . thro ughput r a te f o r p o wer - d o w n m o de microproc e ssor and dsp inter f acing the s e r i al in ter f ace o n t h e ad7 440/ad7450 a al lo ws th e p a r t s to b e dir e c t ly co nn e c te d to man y dif f er en t micr o p r o cess o r s. this s e c t ion ex p l a i n s h o w t o in t e r f ace the ad7 440/ad7450 a wi t h s o m e o f t h e m o r e com m on micr o c on t r ol ler and ds p s e r i a l in ter f ace p r oto c ols. a d 74 40/ a d 7 4 50a to a d s p -2 1xx the ads p -21xx fa mil y o f ds p s is in t e r f ace d dir e c t l y t o th e ad7440/ad74 50a wi t h o u t an y g l ue log i c r e q u ir ed . the s p or t con t r o l r e g i ster sh ou ld b e s e t u p as fol l o w s: t f sw = rfsw = 1 al t e r n a t e f r a m in g invrfs = inv t fs = 1 a c ti v e lo w f r a m e sig n al d t yp e = 00 rig h t-j u s t if y da ta s l en = 1111 16-b i t da ta-w o r ds i s c l k = 1 i n t e rn al se rial c l oc k t f sr = r f sr = 1 fr ame e v e r y word irfs = 0 itfs = 1 t o im p l em en t p o w e r - do wn m o de , s l en s h o u l d b e s e t t o 1001 to issu e an 8 - bi t s c l k b u rst. the co nn ec tion dia g ra m is sh own in f i gur e 45. the ads p -21xx h a s th e t f s a n d r f s o f th e s p o r t ti e d t o g e t h e r , w i t h t f s set as a n o u t p ut and rfs s e t as a n i n p u t. t h e dsp o p era t es in a l ter n a t e f r a m ing m o de and t h e s p or t con t r o l r e g i ster is s e t up a s d e s c r i b e d. t h e f r am e s y nc h r on i z a t i o n s i g n a l ge ne r a te d o n th e t f s i s ti e d t o cs and, a s w i t h a l l s i g n a l pro c e s s i ng a p plic a t ion s , e q uidist an t s a m p li n g is ne cess a r y . h o w e v e r in t h is exa m ple , t h e t i m e r i n t e r r u p t is us e d t o co n t r o l t h e s a m p lin g ra te o f t h e a d c; u nder cer t a i n condi t i on s, e q uidi st a n t s a m p li n g m a y n o t be a c h i ev ed . the t i m e r r e g i s t ers, fo r e x a m ple , a r e lo ade d wi t h a val u e t h a t p r o v ides a n in te r r u p t a t t h e r e quir e d s a m p le in ter v a l . w h e n a n in t e r r u p t is r e ce i v e d , a v a l u e is t r a n smi t t e d wi t h tfs/dt (ad c co n t r o l w o r d ). the tfs is us e d t o co n t r o l t h e rfs a nd t h er efo r e th e r e a d i n g o f da ta . th e f r eq ue n c y o f th e se ri al cloc k i s se t in t h e sc lkd i v reg i s t er . w h en t h e in s t r u c t io n t o t r a n smi t w i t h tfs is g i v e n (a x0 = t x 0), t h e s t a t e o f t h e s c l k is che c k e d . th e ds p wai t s u n t i l t h e sc lk ha s go n e h i g h , lo w , and hig h a g a i n b e fore st ar t i ng t r ans m i s s i on . i f t h e t i m e r a n d s c l k v a lu e s are c h ose n s u c h tha t th e i n s t r u cti o n t o tra n sm i t o c cur s o n o r n e a r th e ri si n g ed ge o f sc l k , th en t h e da ta m a y be tra n sm i t t e d o r i t ma y wai t un t i l t h e n e x t clo c k e d ge. 03051-a - 045 ad7440/ ad7450a* adsp-21xx* sclk dr rfs tfs sclk sdata cs *additional pins removed for clarity f i g u re 45. inte r f a c i n g to t h e a d s p - 21x x f o r exa m p l e , th e ads p -2111 has a mas t er c l o c k f r eq uen c y o f 16 mh z. i f t h e sclkd i v r e g i st er is lo ade d wi t h t h e val u e 3, a n sclk o f 2 mh z is ob t a i n e d and eig h t mas t er cl o c k p e r i o d s e l a p s e fo r e v er y sclk p e r i o d . i f t h e t i mer r e g i s t ers a r e lo ade d wi t h t h e val u e 8 03, th en 100.5 s c lks o c c u r betw een in t e r r u p ts and su bs e q u e n t ly b e twe e n t r ans m i t i n st r u c t ions . this s i t u a t ion r e su l t s in n o n e quidist a n t s a m p li n g as t h e t r a n s m i t i n st r u c t io n is o c c u r r in g o n a sclk e d g e . i f th e n u m b er o f sclks betw een in t e r r u p ts is a w h ole i n t e ger f i g u r e o f n, e q uidi st a n t s a m p lin g i s i m p l em en t e d b y th e ds p .
ad7440/ad7450a rev. b | page 26 of 28 a d 74 40/ a d 7 4 50a to tms 3 20 c5x/ c5 4x the s e r i al in ter f ace o n t h e t m s 320c5x/c54x us es a co n t in uo u s s e r i al c l o c k and f r a m e sy n c hr o n iza t io n sig n als t o syn c hr o n ize t h e da t a t r an sfer o p era t io n s w i t h p e r i ph eral de vices li k e t h e ad7440/ad74 50a. the cs in p u t a l lo ws e a sy in t e r f acin g betw een t h e tms320c5x/c54 x a n d t h e ad74 40/ad7450 a w i th o u t a n y gl u e l o gi c r e q u i r ed . t h e se ri al po r t o f th e t m s320c5x/c54x is s e t u p t o o p era t e in b u rs t m o de wi t h in t e r n al clkx ( t x ser i al c l o c k) a n d fsx (t x f r a m e sy n c ). t h e s e r i al p o r t co n t rol r e g i s t er (s pc ) m u s t ha ve the f o l l o w in g s e t u p: fo = 0, fs m = 1, m c m = 1, a n d t x m = 1. th e f o r m a t b i t, fo , ma y b e s e t t o 1 to s e t t h e w o r d len g t h t o eig h t b i ts i n o r der t o im p l em en t t h e p o w e r - do wn mo de o n t h e ad7 440/ad7450 a. the co n n e c t i on di ag r a m is show n in f i gur e 46. f o r sig n a l p r oce s si n g a p p l ica t i o n s , i t i s im pe ra ti v e th a t th e f r a m e syn c hr o n iza t ion sig n al f r o m th e t m s320c5x/c54x p r o v ide eq ui d i s t a n t sa m p l i n g . ad7440/ ad7450a* tms320c5x/ c54x* clkx dr fsx fsr sclk sdata cs clkr 03051-a - 046 *additional pins removed for clarity f i g u re 46. inte r f a c i n g to t h e tm s 3 2 0 c 5 x / c5 4 ad7440/ad7450a t o dsp56xxx the co n n e c t i on di a g r a m i n f i g u r e 47 sh o w s h o w t h e de vic e can b e co nne c t e d t o t h e sy n c hr o n ous s e r i al in ter f ace (ss i ) o f t h e ds p56xxx fa m i ly o f ds p s f r o m m o t o r o la . th e ss i is o p era t ed in s y nc h r onou s m o d e ( s y n bit i n c r b = 1 ) w i t h i n te r n a l ly g e n e r a t e d 1-w o r d f r a m e sy n c fo r bo th tx an d rx (b i t s fs l1 = 0 a nd fs l0 = 0 in crb). s e t t h e wo r d len g th t o 16 b y s e t t in g bi ts wl1 = 1 an d wl0 = 0 in cra. t o im p l em en t p o w e r - do wn m o de o n t h e ad7440/ad7450a, th e w o rd length can b e c h a n g e d t o 8 b i ts b y s e t t ing b i ts wl1 = 0 an d wl0 = 0 in cra. f o r sig n a l p r o c essin g a p plic a t ion s , i t is i m p e r a t i v e t h a t t h e f r ame s y nch r on i z a t i o n s i g n a l f r om t h e d s p 5 6 x x x prov i d e eq ui d i s t a n t sa m p l i n g . ad7440/ ad7450a* 03051-a - 047 dsp56xxx* sclk srd sr2 sclk sdata cs *additional pins removed for clarity f i g u re 47. inte r f a c i n g to t h e ds p 56x x x grounding and laout hints the p r in ted cir c ui t bo a r d tha t ho us es th e ad74 40/ad7450 a sh o u ld b e desig n e d s o t h a t t h e a n a l o g a nd dig i t a l s e c t io n s a r e s e p a r a te d and c o nf in e d to cer t ain a r e a s o f t h e b o a r d . this faci li t a t e s t h e us e o f g r o u n d plan es t h a t c a n b e e a si l y s e p a ra t e d . a minim u m et ch t e chniq u e is gen e ral l y b e s t fo r g r o u n d pl an es as i t g i ves t h e b e st shi e lding. dig i t a l and a n a l og g r o u n d pl an es shou l d b e j o i n e d in on ly one pl ac e, a st ar g r ou nd p o i n t es ta b l ish e d as c l os e t o th e g n d p i n on the ad7 440/ad7450 a as p o ssib le. a v oi d r u nnin g d i g i t a l lin e s u n d e r t h e de vices b e ca us e t h is c o u p les n o is e on to t h e die . th e analog g r o u n d p l an e sh o u ld be al lo w e d t o r u n un der t h e ad74 40/ad7450 a t o a v oi d noi s e c o upl i ng . t h e p o we r supply l i ne s to t h e ad7440/ad74 50a sh o u ld us e as la rg e a trac e as p o s s ib le t o p r o v ide lo w im p e dan c e p a t h s and r e d u ce t h e ef fe c t s o f g l i t ch es on t h e p o we r sup p ly l i ne. f a s t s w i t c h in g s i g n als lik e c l o c ks s h o u ld b e s h ielde d wi t h dig i ta l g r ou nd to a v oi d r a d i a t i n g noi s e to ot he r s e c t i o n s of t h e b o ard, a nd clo c k sig n a l s sh o u ld ne ver r u n ne a r t h e a n a l o g in p u ts. a v oi d c r o s s o ve r of d i g i t a l a n d a n a l o g s i g n a l s . t r a c e s on opp o s i t e sides o f t h e b o a r d sh o u l d r u n a t r i g h t a n g l es to e a ch o t h e r . this r e d u ce s th e e f f e ct s o f f eed th r o ugh th r o ugh t h e boa r d . a m i cr o- st r i p te chni qu e is b y f a r t h e b e st b u t is not a l wa y s p o ss ibl e w i t h a do ub l e -side d b o a r d . i n t h is te chni q u e, t h e com p on e n t side o f t h e b o a r d is de d i c a te d t o g r o u n d pl an e s w h i l e sig n a l s ar e place d on t h e s o lder side. g o o d de co u p lin g is als o im p o r t a n t. al l a n alog s u p p lies sh o u ld be deco u p led wi th 10 f tan t al um ca pa c i t o r s in pa r a ll e l wi th 0.1 f ca p a ci t o rs t o gnd . t o ac hiev e t h e bes t f r o m th es e de co u p lin g com p o n e n ts, t h e y m u st b e place d as clos e as pos s i b l e t o th e d e v i c e . evaluating the ad7440/ad7450 a performa nce the e v a l u a t i on b o a r d p a ck a g e i n cl udes a f u l l y ass e m b le d and teste d e v a l u a t i on b o a r d , d o c u men t a t io n, and s o f t wa r e fo r co n t r o l l in g t h e b o a r d f r o m a p c v i a t h e e v a l ua t i o n b o a r d co n t r o l l er . th e e v al ua t i on b o a r d co n t r o l l er ca n b e us e d in co n j u n c t io n wi t h the ad7440/ad7450a eval u a tio n bo a r d , as w e ll a s m a n y o t h e r a n al og d evi ce s ev al ua ti o n boa r d s en d i n g wi t h t h e cb desig n a t o r , to de mo n s t r a t e an d e v a l u a t e t h e ac and dc p e r f o r ma n c e o f th e ad7440/ad7450a. the s o f t wa r e al l o ws t h e us er t o p e r f o r m ac (fas t f o ur ier t r ans f or m ) and d c ( h i s to g r am of c o d e s ) te st s on t h e d e v i c e . s e e th e ad7440 /ad7450a a p p l ic a t io n n o t e tha t acco m p a n ies t h e e v a l u a t i on k i t fo r mo r e info r m a t io n.
ad7440/ad7450a rev. b | page 27 of 28 outline dimensions 13 5 6 2 8 4 7 2. 9 0 bs c pin 1 1. 6 0 bs c 1. 95 bs c 0. 65 bs c 0. 3 8 0. 2 2 0. 15 m a x 1. 3 0 1. 1 5 0. 9 0 sea t i n g pl a n e 1. 4 5 m a x 0. 22 0. 08 0. 60 0. 45 0. 30 8 4 0 2. 80 b s c compliant to jedec standards mo-178ba f i g u re 48. 8-l e ad s m a l l o u t l i n e t r ans i s t or p a ck ag e [so t - 23] (r t - 8) di me nsio ns sho w n i n mi ll im e t e r s 0.80 0.60 0.40 8 0 4 85 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa f i g u re 49. 8-l e ad m i ni s m al l o u t l ine p a ck ag e [m sop ] (rm-8) di me nsio ns sho w n i n mi ll im e t e r s
ad7440/ad7450a rev. b | page 28 of 28 ordering guide model temperature range linearity error (lsb) 1 package option 2 branding ad7440brt-reel7 C40c to +85c 0.5 rt-8 ctb ad7440brt-r2 C40c to +85c 0.5 rt-8 ctb ad7440brm C40c to +85c 0.5 rm-8 ctb ad7440brm-reel7 C40c to +85c 0.5 rm-8 ctb ad7450abrt-reel7 C40c to +85c 1 rt-8 csb ad7450abrt-r2 C40c to +85c 1 rt-8 csb AD7450ABRM C40c to +85c 1 rm-8 csb AD7450ABRM-reel7 C40c to +85c 1 rm-8 csb eval-ad7440cb 3 evaluation board eval-ad7450acb 3 evaluation board eval-control brd2 4 controller board 1 linearity error here refers to integral nonlinearity error. 2 rt = sot-23; rm = msop 3 this can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 4 evaluation board controller. this board is a complete unit allo wing a pc to control and communicate with all analog devices e valuation boards en ding in the cb designator. for a complete evalua tion kit, order the adc evalua tion board (that is, the eval-a d7450acb or eval-ad7440cb), the e val-control brd2, and a 12 v ac transformer. see the ad7440/ad7450a applic ation note that accompan ies the evaluation kit for more information. ?2004 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03051-0-2/04(b)

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